1. Field of the Invention
This invention relates generally to computer systems implementing interrupts, and more particularly to methods for generating interrupts in a host adapter for transferring data to host computer.
2. Description of the Related Art
Modern computer systems often utilize one or more buses to connect to peripheral devices to enhance its resources. For example, the resources of a computer system may be substantially increased by attaching one or more peripheral devices such as disk drives, tape drives, printers, scanners, optical drives, CD-ROM, DVD-ROM, and the like. Generally, the peripheral devices are attached to the computer system by means of a bus (e.g., cable).
One of the most popular buses is the well known small computer systems interface (SCSI) bus, which is defined in conformity with SCSI protocols (e.g., SCSI-1, SCSI-2, SCSI-3, etc.), which are incorporated herein by reference. The SCSI protocols are designed to provide an efficient peer-to-peer I/O interface between a host computer system and its peripheral devices. A SCSI bus may accommodate a plurality of SCSI devices up to :a number equal to the number of data bits in the SCSI bus. For example, the narrow SCSI-2 bus may accommodate up to eight devices, of which one is usually a SCSI host adapter.
The SCSI host adapter is typically provided between a processor and one or more SCSI devices ito facilitate transfer and conversion of data and control signals. FIG. 1 illustrates a block diagram of an exemplary computer system 100 having a host computer 102 coupled to a plurality of SCSI devices 112 by means of a SCSI bus 114. The host computer 102 includes a host bus 104, a processor 106, a memory 108, and a SCSI host adapter 110. The processor 106 is coupled to the bus 104 (e.g., ISA bus, EISA bus, PCI bus, etc.) for processing information such as data and instructions. The memory 108 is also coupled to the bus 104 for storing and providing information for the processor 106. Although the bus 104 is shown to connect directly between the processor 106 and memory 108, other configurations with a different processor/memory and bridge to the bus 104 are also possible implementations.
The SCSI host adapter 110 is coupled between the bus 104 and the SCSI bus 114 to interface and communicate information between the host computer 102 and the SCSI devices 112. Under the current SCSI specifications, the SCSI bus 114 may interconnect up to 7 or 15 target SCSI devices 112 to the host adapter 110 depending on the type of SCSI bus implemented. The target SCSI devices 112 may be devices such as disk drives, tape drives, printers, scanners, optical drives, or any other devices that meet the SCSI specification.
The host adapter 110 provides interface functions and controls communication between the host computer 102 and the SCSI devices 112 using interrupts. Specifically, the host adapter 110 is configured to receive data, address, and control signals from the host computer 102 via the host bus 104 and convert the signals into corresponding SCSI compatible data, address, and control signals. Conversely, the host adapter 104 is also configured to receive SCSI compatible data, address, and control signals from the SCSI devices 112 through the SCSI bus 114 and convert them into corresponding host-bus compatible data, addressing, and control signals. The SCSI host adapter 110 is well known in the art and may be implemented, for example, by using AIC-7890A(trademark) packaged semiconductor device, which is available from Adaptec Inc., of Milpitas, Calif.
As is well known in the art, the communication between the processor 106 and the SCSI devices 112 occurs over various bus phases as defined by SCSI standards. FIG. 2 shows an exemplary timing diagram 200 of SCSI bus tenancies 228 and 230 involved in transferring data between the host adapter 110 and a selected SCSI device 112. For an I/O operation such as reading data from the selected SCSI device 112 to the processor 106, for example, the processor 106 issues a READ command to the host adapter 110. The host adapter 110 then arbitrates for the SCSI bus 114 during an arbitration (ARB) phase 202. After gaining arbitration, the host adapter 110 selects the selected SCSI device 112 as the target in a selection (SEL) phase 204. At this time, the target receives the SCSI ID of the host adapter 110 so that it may reselect the host adapter 110 in a reselect phase.
Once the target has been selected, the host adapter 110 provides, during a message tag (MSG TAG) phase 206, a message to the target identifying the specific command transferred during this selection for future reference by the target. The host adapter 10 then issues the READ command to the selected target during a COMMAND (CMD) phase 208. Then, the communication between the host adapter 110 and the target is typically terminated in a message disconnect (MSG DISC) phase 210 to allow other devices access to the bus. At this time, the SCSI bus enters into a bus free phase 212 indicating the end of the command phase and the availability of the SCSI bus for other devices. The phases 202 to 210 are commonly known as command tenancy 228.
Following the bus free phase 212, the selected SCSI device re-establishes connection with the host adapter 110 to continue the interrupted transaction for transferring data during data tenancy 230. Specifically, the selected SCSI device arbitrates for the bus in an arbitration phase 214 and then reselects the host adapter, which functions as a target, during a reselection (RE-SEL) phase 216. Then, the target sends a reconnect message (MSG RECON) 218 followed by a tag message (MSG TAG) 220 in a message phase. This informs the host adapter 110 which command the following data and status phases are for. Then, data is transferred from the selected SCSI device to the host adapter 110 for use by the host processor during a data phase 222. During a following status (STATUS) phase 224, the SCSI device provides well known status information to the host adapter 110 to indicate success or failure of the command. When the status phase 224 ends, the SCSI device passes a command complete (CMD COMP) message in a command complete phase 226 to indicate that the command has been completed. Following the command complete phase 226, the SCSI bus again enters into another bus free phase. The phases 214 to 226 are often called data tenancy 230.
In conventional computer systems, a host adapter typically generates an interrupt signal at the end of the I/O command complete phase 226 and sends the signal to the processor. This signal informs the processor that the previously requested data have been transferred, for example, via a DMA transaction. The interrupt signal interrupts the processor from its current task and causes the processor to make use of the transferred data.
Given that processors in modern computer systems are highly pipelined, interrupt reception can cause a substantial loss of useful computation time, thereby resulting in reduced system throughput. Hence, it is desirable to reduce the number of interrupts to a minimum required for adequate responsiveness. For SCSI host adapters, this has involved reducing the number of interrupts to a fraction of the number of I/O command completions.
A widely used technique called xe2x80x9cinterrupt batchingxe2x80x9d reduces interrupts by batching (i.e., accumulating) a number of I/O command completions together to generate a single interrupt. For example, this approach waits a specified period of time after completion of a task (i.e., command completion) to determine if any more tasks are completed. It may also wait for a specified number of command completions. In either case, this technique monitors the command completions for the specified duration or number. An interrupt is then asserted either, after the expiration of the specified period or upon reaching the specified number of completions, whichever occurs first.
Unfortunately, while this method may reduce the number of interrupts, it often adds substantial latency in processing. For example, in a SCSI bus setting where only up to seven or fifteen target devices are attached to the bus, the rate of command completions is typically low. The low rate of command completion, in turn, means that the accumulation of sufficient number of commands will take a substantial amount of time. Waiting for an interrupt, until sufficient number of commands has been completed, thus delays the execution of programs that require I/O data from the SCSI devices.
Even in the case of generating an interrupt after a specified period of time, the low rate of command completions typically leads to an accumulation of a correspondingly low number of command completions for generating an interrupt. In addition, when no additional commands are completed within the specified period, the generation of interrupt is delayed until the end of the period. Hence, latency results from having to wait for the period to expire. The latencies thus degrade overall performance of the computer system.
In view of the foregoing, what is needed is a method for generating interrupts so that the number of interrupts are substantially reduced without incurring additional latency.
The present invention fills these needs by providing contention-based methods for generating reduced number of interrupts from a host adapter. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, a method, or a computer readable medium. Several inventive embodiments of the present invention are described below.
In one embodiment, the present invention provides a method for generating reduced number of interrupts upon completing one or more commands. Each interrupt indicates that data has been transferred from a host adapter to a processor. The host adapter is coupled to one or more I/O devices over a bus. One or more I/O commands are received for transferring data between the processor and one or more I/O devices. Then, the contention for the bus among the I/O devices is monitored to determine how many devices are arbitrating for the bus. If only one of the devices is contending for the bus, the one device transfers data to the host adapter. On the other hand, if a plurality of devices is contending for the bus, the plurality of devices are eventually selected and transfers data to the host adapter until all of the plurality of devices have been selected and associated data transferred to the host adapter. An interrupt is then asserted to the processor for the one device or the plurality of devices such that one interrupt is used to indicate that one device or the plurality of devices has transferred data, thereby reducing the number of interrupts when more than one devices are contending for the bus.
In another embodiment, the present invention provides a method for generating an interrupt upon completing one or more commands from a processor. The processor is coupled to a host adapter that is coupled to one or more I/O devices via a bus. The interrupt indicates completion of data transfer to or from one or more I/O devices. The method includes: (a) receiving and completing one or more commands for transferring data to or from one or more I/O devices over the bus; (b) after completing a selected command, waiting a first specified period of time to determine whether a first I/O device is arbitrating to reselect the host adapter for transferring first data to or from the first I/O device in accordance with a first command; (c) if, after the first specified period of time, no I/O device is arbitrating to reselect the host adapter, posting an interrupt to the processor to indicate the completion of previous data transfer completions; and (d) if, after the first specified period of time, the first I/O device is arbitrating to reselect the host adapter; (d1) transferring the first data to or from the first I/O device and waiting for the first data transfer to be completed; and (d2) upon completion of the first data transfer, asserting a first completion of the first command, wherein the completions of the first and selected commands are accumulated for subsequently generating one interrupt to indicate the accumulated completions. Preferably, the waiting is just long enough to determine if there is a reselection in contrast to conventional technique of waiting until another command is completed.
In yet another embodiment, a method is disclosed for generating an interrupt upon completing one or more commands from a processor. The interrupt indicates completion of data transfer to or from a host adapter, which is coupled to one or more I/O devices over a bus. One or more I/O commands for transferring data to or from one or more I/O devices are received and completed. Upon completing each command, the host adapter waits a specified iterations of a loop counter to determine whether the host adapter has been re-selected by an I/O device for transferring data to or from the I/O device. If the host adapter is re-selected by the I/O device, data is transferred to or from the reselecting I/O device without generating an interrupt so as to batch data transfer completions. If the host adapter is not reselected, an interrupt is posted to the processor to indicate the accumulated data transfer completions. Preferably, the loop counter is reset whenever the interrupt is posted.